CoWoS-L Moves Beyond Reticle Limits as AI Chips Add More Compute Dies and HBM Stacks

Package area becomes a design constraint

TrendForce reported on September 18, 2026 that GPU suppliers and hyperscale cloud providers are making larger package sizes a priority for 2.5D integration. AI accelerators now combine more compute dies, more HBM stacks and wider interfaces. Conventional CoWoS-S uses a silicon interposer to connect those elements at high density, but the interposer is approaching practical exposure and manufacturing limits as designs grow.

The constraint is broader than physical area. Each additional die or HBM stack changes routing, power delivery, thermal density, substrate warpage, known-good-die matching and final test requirements. Package value and loss exposure rise together because a defect late in assembly can strand several expensive components. Advanced packaging therefore acts as an architectural gate rather than a downstream assembly choice.

The boundary between CoWoS-S and CoWoS-L

TrendForce describes CoWoS-S as capable of integrating two SoCs or chiplets and eight HBM modules. That structure is expected to remain suitable for ASICs such as Microsoft Maia 200. Designs requiring more compute dies or memory stacks need a different geometry. CoWoS-L embeds high-speed silicon bridge dies within a larger interposer structure, concentrating fine-pitch connections where they are needed while allowing a larger package footprint.

NVIDIA and AMD AI accelerators already use CoWoS-L. Meta MTIA 400 also uses the technology, and AWS and Microsoft are expected to adopt it in 2027. Those design wins establish a production direction, but they do not create a standard interchangeable bill of materials. Die count, HBM generation, bridge placement, substrate stack-up and test coverage remain platform-specific.

HBM expansion creates linked bottlenecks

Adding HBM increases bandwidth and capacity, but it also expands power, cooling and routing demands. Interposer density, microbump pitch, substrate layers and power integrity must move together. A shortfall in one parameter can force lower frequency, fewer interfaces or a delayed qualification cycle. HBM availability alone does not guarantee a shippable accelerator.

The procurement unit is therefore the qualified package configuration, not an isolated compute die or memory stack. Supply depends on assembly slots, known-good-die matching, package yield, final test and OEM platform validation. Inventory in one component cannot automatically substitute for a missing capacity window elsewhere in the package flow.

EMIB-T competes through localized bridges

Larger CoWoS-L structures raise package cost, while constrained TSMC capacity creates an opening for Intel EMIB. EMIB reduces reliance on a large full silicon interposer by embedding local silicon bridges in the package substrate. The potential advantage is lower interposer area and cost. The tradeoff is that overall performance depends more heavily on substrate routing density.

Intel has been improving line-and-space and microbump specifications and is developing EMIB-T with through-silicon vias. TSVs shorten signal paths and improve module performance. TrendForce expects Google to adopt EMIB-T in 2027, while AWS is testing EMIB. A move between CoWoS-L and EMIB-T still requires architectural changes, new package design rules and a fresh qualification path.

Demand reaches several packaging routes

TrendForce expects NVIDIA high-end GPU shipments to grow about 30% year over year in 2026. AMD is pushing the MI400 and MI450 families from the second half of 2026. Google TPU v7 is expected to lead cloud-developed ASIC volume and growth, while AWS systems move toward Trainium v3. Microsoft and Meta remain more dependent on GPU servers, although their custom silicon plans continue.

This demand mix loads CoWoS-L, CoWoS-S and competing bridge technologies differently. A GPU platform with many HBM stacks cannot be mapped directly onto a smaller inference ASIC. Capacity announcements should be read by process, package family, qualified customer and ramp phase. Nominal wafer or assembly capacity is not the same as output at target yield.

Qualification defines the 2027 window

TrendForce expects CoWoS-L to remain the mainstream AI packaging technology through 2028 because of maturity and yield. The relevant 2027 evidence includes production ramp rates, substrate supplier qualifications, HBM configurations, thermal limits, reliability results and final-test throughput. Public adoption plans mark design direction; committed production dates and qualified part configurations mark supply.

EMIB-T can capture programs where cost and interposer area matter, but its substrate routing and ecosystem maturity need platform evidence. CoWoS-L retains a larger installed base and established yield learning. The two routes are likely to coexist because cloud ASICs, GPUs and rack-scale systems place different priorities on density, cost, schedule and supplier concentration.

Procurement boundaries remain product-specific

Advanced packaging tightness does not imply a universal shortage across semiconductor packaging. CoWoS-L primarily serves large AI accelerators and selected cloud ASICs. Analog ICs, MCUs, power devices and most consumer components use different assembly lines and materials. Price and lead-time conclusions must stay tied to a specific package architecture and customer program.

The most useful checkpoints are qualified CoWoS-L ramp capacity, substrate readiness, HBM stack count, EMIB-T tape-outs, final-test expansion and OEM platform launches. AI package supply is increasingly determined by synchronized yield across several expensive components. That shift makes configuration-level evidence more valuable than aggregate capacity claims.